Self-Testing of FPGA Delay Faults in the System Environment
نویسنده
چکیده
We propose a procedure for self-testing of an FPGA programmed to implement a user-defined function. The procedure is intended to improve the detectability of FPGA delay faults. This improvement is obtained by modifying the functions of LUTs in the section under test, so that each LUT implements a XOR function. We show that, despite many potential problems, the proposed modification can significantly enhance the susceptibility of FPGA delay faults to random testing.
منابع مشابه
Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs
We present an extension of a procedure for self-testing of an FPGA that implements a user-defined function. This extension, intended to improve the detectability of FPGA delay faults, exploits the reconfigurability of FPGAs and is based on modifying the functions of LUTs in the section under test. A modification procedure replaces a user-defined function of each LUT with a specific function tha...
متن کاملEmbedded Memory Test Strategies and Repair
The demand of self-testing proportionally increases with memory size in System on Chip (SoC). SoC architecture normally occupies the majority of its area by memories. Due to increase in density of embedded memories, there is a need of self-testing mechanism in SoC design. Therefore, this research study focuses on this problem and introduces a smooth solution for self-testing. In the proposed m...
متن کاملTiming Defect Analysis in Look-Up Tables of SRAM-Based FPGAs
The objective of our article is to demonstrate that some physical defects in a LUT can change its propagation delay. We propose a simplified 'timing' model of the LUT which determines its propagation delay. Such a model is exploited to analyse the effects of a defect on the LUT behaviour, from which we demonstrate that they can cause a timing fault on it. Anywhere in a LUT, a timing defect can ...
متن کاملSelf-Stabilization Testing of LUT-Based FPGA Designs by Fault Injection
New testing methods are required as the complexity of Field Programmable Gate Array (FPGA) designs grow rapidly and time-to-market demands shorten. In this paper we propose a new, physical fault injection method for the test of a system’s self-stabilizing property, that is its intrinsic ability to recover from transient faults. Therefore we inject transient faults in Look-Up Table (LUT)-based F...
متن کاملDefect Analysis for Delay-Fault BIST in FPGAs
Detecting delay faults in SRAM-FPGAs can be done resorting to BIST. In this context, the objective of this paper is to analyse the timing behaviour of Look-Up Tables (LUT) contained in FPGAs in both fault-free and delay faulty cases. We first show that the propagation delay of a LUT depends both on the transition pattern applied to its inputs and on the function implemented in it. This signific...
متن کامل